IR drop is becoming an increasingly important problem for semiconductor manufacturers as semiconductor technology, particularly CMOS technology, scales down to 0.13 μm and below. Chips can be designed that utilize tens of millions of transistors, parasitic resistors, and capacitors. Each of these transistors has to be supplied through a power grid with a proper supply voltage. Since the density of chips and systems continues to increase for Deep Submicron Designs (DSMD), the IR drop problem can lead to unreliable or malfunctioning chips, regardless of whether a DRC/LVS process (Design Rule Checking/Layout vs. Schematic process for high accuracy verification of design rules) is done successfully.
The concept of “IR drop” refers to a drop in the main supply voltage (VDD) that can occur along the power rails between the power pads, the ground pads, and the logic components of a chip. As the geometries get smaller, so too do the supply voltages, currently pushing down to about 1V, such that the tolerance for drops in supply voltage becomes much tighter. As the IR drop to supply voltage ratio increases, the DC noise tolerance of the CMOS transistors on the chip degrades and the switching speeds acquire increased timing delays. A significant IR drop can lead to a timing violation in static logic and/or a functional failure in dynamic logic. Meeting the timing specification is critical for a successful design. Therefore, precise full-chip IR drop analysis and correction is becoming a necessary step in the full-chip design process.
Various simulation tools can be used to determine IR drop. It is not sufficient to simply determine average voltage drops, however, and it is necessary to evaluate the effects of decoupling capacitance used in the industry to fight IR drop. Due to the previous lack of reliable and accurate methods of predicting IR drop, preventative measures have primarily been used in existing systems. Such approaches involve, for example, using a more conservative design and layout approach, using additional metal layers to reduce IR drop, and/or providing additional voltage lines. Each of these approaches can increase costs and reduce performance, such that they do not provide optimal solutions to the problem of IR drop.